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1. (jCommunity Group) Tuesday, 31 December 2069 2. SystemC and Transaction-Level Modeling (TLM) (MyBlog/TB-Blog) ... to an Engineer? Team? Company? When first adopting SystemC, who are the typical first users? Designers? Verification Engineers? Architects? Others? Are there more standards that are needed to fuel SystemC ... Monday, 21 December 2009 3. Processor Design: System-On-Chip Computing for ASICs and FPGAs (MyBlog/TB-Reviews) ... arose almost daily. The, through the 1990s, processor design centralized around a few major players, including Intel, AMD, and TI - the ones who could afford the design, verification, and foundry costs ... Friday, 18 September 2009 4. Interview Bites: Metro Ethernet Forum's Nan Chen on Carrier Ethernet (MyBlog/TB-Articles) ... Global Interconnect? Nan Chen: It consists of the actual technical specifications, the standards, verification, and the operational processes that we're working on to enable the smooth transition from ... Monday, 02 November 2009 5. Formal is more than just alive and well. It is thriving! (MyBlog/TB-Articles) ... of innovation in formal verification core techniques?” This just did not sound right to me and I made several comments in response to this, but I thought I should do more of a well thought out response ... Friday, 12 February 2010 6. Wow! Latest Cadence Encounter Digital Implementation System is mind-boggling! (MyBlog/TB-Blog) ... to be absolutely mind-boggling. The folks at Cadence have just released their Cadence Encounter Digital Implementation (EDI) System 9.1, a complete and integrated digital design, implementation, and verification ... Monday, 01 February 2010 7. Hot News - Synopsys acquire CoWare! (MyBlog/TB-Blog) ... from our very own Brian Bailey in the TechBites ESL and Verification communities. ... Monday, 08 February 2010 8. Hot New Release of Allegro and OrCAD from Cadence (MyBlog/TB-Blog) ... include increasing productivity and predictability, and also in-process analysis and verification for compliance). And being environmentally aware involves using ecologically-friendly parts, lowering power ... Wednesday, 28 October 2009 9. Synopsys and CoWare tie the knot. Virtual Prototyping on fire!! (MyBlog/TB-Blog) ... an about CoWare section, and second release from Synopsys that has a quote from them and an about Synopsys. Synopsys says "System-level design and verification solutions have been gaining traction among ... Monday, 08 February 2010 10. Xilinx launch New Connectivity, Embedded, and DSP Kits (Nitty-Gritty Details) (MyBlog/TB-Articles) ... steps, design creation, and verification. Connectivity Platforms Xilinx serial and parallel connectivity solutions are designed to meet the most demanding bandwidth, power, and cost requirements for bringing ... Tuesday, 08 December 2009 11. SystemC and TLM (Q&A #1) (MyBlog/TB-Blog) ... first question: "Is SystemC and TLM a mainstream methodology in the market today?" Question #1: Is SystemC and TLM a mainstream methodology in the market today? Verification and Design Languages SystemC ... Monday, 21 December 2009 12. Welcome to TechBites (MyBlog/TB-Articles) ... of the ESL and Verification communities). What's the algorithm behind the Karma points? I don’t know. Trust me, I've tried to find out, but those who don the undergarments of authority and stride the ... Wednesday, 11 November 2009 13. Creating an Open Source-based FPGA Design Flow (MyBlog/TB-Articles) ... what you are doing with regards to creating digital logic designs, starting a successful FPGA design house requires a few fundamental pieces: A development platform, A verification environment Formal ... Tuesday, 05 January 2010 14. Education is possibly the largest issue facing EDA (MyBlog/TB-Blog) ... Verification Time and Effort. I listened to the first panel, and moderated the second one. One of the biggest take-aways for me, and this came as a surprise is that both the end users and the EDA companies ... Friday, 26 February 2010 15. White paper review: Zocalo Enabling Assertion Based Verification (MyBlog/TB-Reviews) Zocalo Tech, a startup concentrating on assertion based verification, has been active recently in terms of their articles, blogs and other activities in the media in an attempt to bring attention to the ... Tuesday, 12 January 2010 16. Mentor embraces SystemC in their Catapult high-level synthesis solution (MyBlog/TB-Articles) ... comprehensive ESL design, verification and synthesis.” Mentor’s users are also praising the move. “Mentor's decision to add SystemC support to a proven high-level synthesis flow with Catapult C synthesis ... Monday, 25 January 2010 17. LFSRs (Part 3) (MyBlog/TB-Articles) ... note below) may benefit from the portrayal of random stimulus such as external interrupts. Random stimulus can result in more realistic design verification, which can uncover problems that may not be revealed ... Sunday, 20 September 2009 18. BDTi, Xilinx, AutoESL and Synfora dispel rumors about high-level synthesis (MyBlog/TB-Articles) ... about 2X in design productivity, somewhat less than most vendors had been claiming, but in addition a 4X gain in verification. Their summary results are shown below. Synfora also provided me with ... Monday, 18 January 2010 19. ESL Verification Languages. What will it be based on? (MyBlog/TB-Articles) In the early days of RTL verification, the Verilog language was perhaps the most likely language to be found being used as a verification language as well. Others preferred the C language because of the ... Monday, 28 December 2009 20. New MIPS uC Cores – 32-bit Performance / 16-bit Code Size (MyBlog/TB-Blog) ... with technology from Carbon Design Systems – for verification in SystemC and co-simulation environments. Software developers can also take advantage of fast instruction set simulators – developed in conjunction ... Monday, 02 November 2009
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