1.
(jCommunity Group)

2. SystemC and Transaction-Level Modeling (TLM)
(MyBlog/TB-Blog)

... to an Engineer? Team? Company? When first adopting SystemC, who are the typical first users? Designers? Verification Engineers? Architects? Others? Are there more standards that are needed to fuel SystemC ...

3. Interview Bites: Metro Ethernet Forum's Nan Chen on Carrier Ethernet
(MyBlog/TB-Articles)

... Global Interconnect? Nan Chen: It consists of the actual technical specifications, the standards, verification, and the operational processes that we're working on to enable the smooth transition from ...

4. Brian Bailey’s must see list for DAC 2010
(MyBlog/TB-Blog)

... and HW/SW integration issues, and ChipEstimate (521) (part of Cadence) for chip estimation and planning. Verification Zocalo Tech (1509) – with their assertion creation and control tools and NextOp ...

5. Processor Design: System-On-Chip Computing for ASICs and FPGAs
(MyBlog/TB-Reviews)

... arose almost daily. The, through the 1990s, processor design centralized around a few major players, including Intel, AMD, and TI - the ones who could afford the design, verification, and foundry costs ...

6. Formal is more than just alive and well. It is thriving!
(MyBlog/TB-Articles)

... of innovation in formal verification core techniques?” This just did not sound right to me and I made several comments in response to this, but I thought I should do more of a well thought out response ...

7. Hot News - Synopsys acquire CoWare!
(MyBlog/TB-Blog)

... from our very own Brian Bailey in the TechBites ESL and Verification communities.  ...

8. Synopsys and CoWare tie the knot. Virtual Prototyping on fire!!
(MyBlog/TB-Blog)

... an about CoWare section, and second release from Synopsys that has a quote from them and an about Synopsys. Synopsys says "System-level design and verification solutions have been gaining traction among ...

9. The fate of NuSym becomes clear
(MyBlog/TB-Blog)

While I have seen no announcements, it becomes clear today that Synopsys has acquired the assets of NuSym, a company that looked as if they had exciting technology a few years back and was one of the early ...

10. Wow! Latest Cadence Encounter Digital Implementation System is mind-boggling!
(MyBlog/TB-Blog)

... to be absolutely mind-boggling. The folks at Cadence have just released their Cadence Encounter Digital Implementation (EDI) System 9.1, a complete and integrated digital design, implementation, and verification ...

11. Is Synopsys getting ready to buy EVE?
(MyBlog/TB-Blog)

... products can extend the benefits of system-level visibility to development teams for hardware-software co-verification." "Adding support for TLM-2.0 gives software developers and hardware verification ...

12. Creating an Open Source-based FPGA Design Flow
(MyBlog/TB-Articles)

... what you are doing with regards to creating digital logic designs, starting a successful FPGA design house requires a few fundamental pieces: A development platform, A verification environment Formal ...

13. Xilinx launch New Connectivity, Embedded, and DSP Kits (Nitty-Gritty Details)
(MyBlog/TB-Articles)

... steps, design creation, and verification. Connectivity Platforms Xilinx serial and parallel connectivity solutions are designed to meet the most demanding bandwidth, power, and cost requirements for bringing ...

14. White paper review: Zocalo Enabling Assertion Based Verification
(MyBlog/TB-Reviews)

Zocalo Tech, a startup concentrating on assertion based verification, has been active recently in terms of their articles, blogs and other activities in the media in an attempt to bring attention to the ...

15. Mentor embraces SystemC in their Catapult high-level synthesis solution
(MyBlog/TB-Articles)

... comprehensive ESL design, verification and synthesis.” Mentor’s users are also praising the move. “Mentor's decision to add SystemC support to a proven high-level synthesis flow with Catapult C synthesis ...

16. BDTi, Xilinx, AutoESL and Synfora dispel rumors about high-level synthesis
(MyBlog/TB-Articles)

... about 2X in design productivity, somewhat less than most vendors had been claiming, but in addition a 4X gain in verification. Their summary results are shown below. Synfora also provided me with ...

17. Synopsys extends its investment in virtual prototypes
(MyBlog/TB-Blog)

Several years ago Synopsys acquired Virtio and started to build a presence in the virtual prototyping market. This coupled well with their acquisition of physical prototyping and I have been eagerly awaiting ...

18. SystemC and TLM (Q&A #1)
(MyBlog/TB-Blog)

... first question: "Is SystemC and TLM a mainstream methodology in the market today?" Question #1: Is SystemC and TLM a mainstream methodology in the market today? Verification and Design Languages SystemC ...

19. Hot New Release of Allegro and OrCAD from Cadence
(MyBlog/TB-Blog)

... include increasing productivity and predictability, and also in-process analysis and verification for compliance). And being environmentally aware involves using ecologically-friendly parts, lowering power ...

20. Education is possibly the largest issue facing EDA
(MyBlog/TB-Blog)

... Verification Time and Effort. I listened to the first panel, and moderated the second one. One of the biggest take-aways for me, and this came as a surprise is that both the end users and the EDA companies ...