Hi all,

I have started with Ray Salemi's "FPGA Simulation" book. A geat one to get started and get a grasp of what is needed and what is available. Also, www.verificationacademy.net is a good resource on introductory material from Mentor. And of course: practice!

JaaC

First off, there is no one right way to do verification. Every design, every group, every company has different priorities, amount they can spend and a different desired quality. If you are designing a childs toy, there are very different verification requirements compared to the verification of a implantable medical device. Intel has a different quality standard compared to most companies because of the impact on their image of errors that creep out. While I hate to call verification an "art", there are aspects of it that are, although careful planning and implementation make it more of a well thought out strategy.

To make the right trade-offs, you have to really understand the basics and I believe the best book for that is an old one now, but still relevant. Writing Testbenches by Janick Bergeron. There are several editions of this available and the best one is the one about SystemVerilog as this creates a more modern and extensible verification framework than earlier editions.

After that, it is probably best to look as some of the verification frameworks, such as OVM or UVM. These too contain lots of information about how to structure the testbench correctly. Then there are lots of books about various languages that may be of use once you have decided on the basic techniques. After that - I think you will know what you need to write some good testbenches. The rest is just practice.

Ravi,
Maybe you are looking for an inhouse "Verification architect" to have frequent discussions. But things like parallel-to-serial block are far easier than the need for such an expert - maybe that was just "an example" you quoted.

In terms to nitty gritties of doing from scratch verification with all modern technologies/methodologies and languages, take a look at UVM/OVM/VMM. Tons of examples are around on the net @ www.uvmworld.org (SoC ref kit), www.ovmworld.org, www.vmmcentral.org

Of-course you need a capable simulator to master these - maybe you have access to it already. If not consider talking to us via www.cvcblr.com/trainings - we do this as a professional service/training with duration being 2 weeks, 4 weeks etc.

Good Luck
Srini
www.cvcblr.com/blog

Hi Gopi,

I have read this site but i need some practical environment Example.
How clock and Reset generation block is created(its not like as mention in site just create one initial block for clock and one initial block for reset)?
There are some consideration for generate generic clock and reset for synchronous and asynchronous systems.

If i have to verify one parallel to serial converter Block then what is step i have to follow for complete verification of this block?

Best Regards:

R@vi

From School days Linear testbecnchs to Todays UVM
are on www.testbench.in