My mind is reeling with the news that the folks at Altera are already talking about their upcoming FPGAs at the 28 nm half-node. Apart from anything else, these little rascals (the FPGAs, not the folks at Altera) will boast transceivers running at 28 Gbps. The mind boggles.

I'm still trying to wrap my brain around all of this. First of all, the "official" industry technology roadmap calls for nodes at 45 nm, 32 nm, 22 nm, and so forth. However, in addition to these "full nodes", some foundries have started to come out with what they refer to as "half nodes". This explains why Altera's current generation of FPGAs and HardCopy ASICs were implemented using a 40 nm process.

Now, it seems that the guys and gals at Altera are going to shun the 32 nm node and leap headfirst into the 28 nm node for their next generation devices. In fact they are talking about all sorts of new innovations that will be incorporated into their upcoming 28-nm FPGAs.

Comparing Density, Power, and Transceiver Count

For example, embedded HardCopy Blocks, a new method for partial reconfiguration, and embedded 28-Gbps transceivers will dramatically improve the density and I/O performance of next-generation Altera FPGAs and further strengthen their competitive position versus ASICs and ASSPs.

The rapid growth of bandwidth-intensive applications such as high-definition (HD) video, cloud computing, online data storage and mobile video has created a challenge for both infrastructure and end-user equipment developers. How can they quickly increase system bandwidth while staying within strict power and cost budgets? Altera has developed its latest innovations to solve these challenges.

The new Embedded HardCopy Blocks are customizable hard intellectual property (IP) blocks that leverage Altera’s unique HardCopy ASIC capabilities. They are used to harden standard or logic-intensive functions such as interface protocols, application-specific functions, and proprietary custom IP. The Embedded HardCopy Blocks offer customers faster time to market for their designs while also reducing cost and power. For Altera, this innovation allows the company to quickly create variant products and target specific market segments.

Partial reconfiguration allows designers to reconfigure part of the FPGA while other sections remain running. This is extremely important in systems where uptime is critical because it allows designers to make updates or adjust functionality without disrupting services. Lowering power and cost, partial reconfiguration also improves effective logic density by removing the necessity to place in the FPGA functions that do not operate simultaneously. Instead, these functions can be stored in external memory and loaded as needed. This reduces the size of the FPGA by allowing multiple applications on a single FPGA, saving board space and reducing power.

To date, partial reconfiguration solutions have been time-intensive tasks that required designers to know all of the intricate FPGA architecture details. Altera is simplifying the partial reconfiguration process by building the capability on top of the existing incremental compile design flow in its Quartus II design software.

Extending its embedded transceiver technology, Altera has developed 28-Gbps embedded transceivers, which will also be implemented in upcoming 28-nm FPGAs. These high-speed transceivers will enable customers to implement next-generation designs such as 400G systems on a single chip without the need for costly external components.