“Verilog is like C, and VHDL is like assembly”

was what someone once (erroneously!) commented to me. It occurred to me perhaps VHDL is for ultimate nerds, geeks, or even aliens, especially when creating models of signal-processing algorithms, RISC Processor modeling, etc.

Thanks to the book ‘The Student’s Guide to VHDL’, this notion soon disappeared. One of the notable features is the ease of flow of the book’s contents. By introducing details step-by-step, and by implementing a software engineering approach, Ashenden tries (and succeeds!) to convey the syntax without hammering with boredom/details. The book starts with basic details and simple examples.

The book is a best-buy because of the syntax introduced. The syntax that Ashenden uses is easier to understand and interpret as compared to what others use, like in the IEEE standard document. It’s note-worthy while differentiating the compulsory parameters from the optional ones.

The ‘Student’s Guide’ is a low-cut version of his ‘Designer’s Guide’. The latter includes topic such as file handling, etc. Also, the section on RISC processor is more detailed. If you are looking for a professional use of VHDL, investing a few bucks more for the ‘Designer’s Guide’ might be a good option. However, for an academic use, the ‘Student’s Guide’ will be sufficient.