The folks at Cadence are jumping up and down with excitement about the release of their Virtuoso IC6.1.4 release. This version of Cadence's high-end analog and mixed-signal chip design platform is replete with capacity, performance, and usability boosts that should help to dramatically reduce overall design time while ensuring high-quality production ICs.

The enhancements in Virtuoso IC6.1.4 will benefit design teams working along the full spectrum of design complexity, from the most advanced-node, cutting-edge designs to more traditional chips.

The new Virtuoso release has been extended to work efficiently at advanced nodes down to 28 nanometers and now supports 64-bit processing for improved capacity and performance. The Virtuoso Space-Based Router has been integrated into the Virtuoso Layout Suite cockpit, making it easier to access. More importantly, it now provides design teams a single common router they can use from start to finish to help ensure consistent results. Additional time-saving, quality-enhancing updates have been made to the Virtuoso Analog Design Environment XL, and Cadence design constraints technology.

Integrating the Virtuoso Space-Based Router into the Virtuoso Layout Suite brings the power of a 1 million net-capable router to the desk of every layout engineer. Interactive wire editing and full chip automatic finish routing share the same algorithms, providing a seamless flow for a higher quality of design, from IP module creation through full chip sign-off.

One thing I found particularly interesting is the data-mining capabilities that Cadence have been using to improve the product. One example aspect if this is to monitor the ways in which multiple users interact with the tools to improve ease-of-use and productivity.

One simple example the folks at Cadence told me about in order to illustrate this point features the use of rulers. It was discovered that users were spending a lot of time measuring the distances between tracks and other structures on the chip. The reason the users were spending so much time was that they had to spend multiple mouse clicks zooming in so as to precisely attach the rulers. Based on this information, the Virtuoso team modified the rulers to automatically attach in an intelligent manner. The result is to limit "mouse miles" and dramatically improve productivity.

Improvements to the Virtuoso Analog Design Environment XL include new display capabilities within the product that can now produce more, and better, datasheets. The ability of Virtuoso Analog Design Environment XL to analyze multiple tests simultaneously, including those across corner and statistical variations, helps engineers pick the best circuit design directions early in the design cycle, and verify those choices efficiently post implementation.

The Cadence design constraints methodology, which can help engineers reduce layout optimization and design refinement times by as much as 20 percent, received a boost in the new release, with enhancements that make it easier to add design constraints. In addition, there are new design constraints specifically geared to address sub-45-nanometer design yield challenges.

The new release extends the Cadence ExpressPcells capability to support multiple-user sites. Now customers can use their vast libraries of SKILL-parameterized cells anywhere and see up to an 8 times performance improvement. Cadence also improved the analog display technology to handle multi-gigabyte waveform files more efficiently and removed the two-gigabyte limit on waveform databases to account for today's larger, more complex designs.

One phrase that I saw in the presentation Cadence gave me was:

Embrace the "What If?" and avoid the "What Now?"

I don’t know why, but this has really stuck in my mind. In fact it's becoming sort of a mantra that I mutter to myself as I wander through my day (like I needed something else rattling around in my brain :-)